1. Field of the Invention
The present invention relates to a semiconductor memory device having continuous mode in which read data is outputted in a continuous manner or write data is inputted in a continuous manner.
2. Description of the Related Art
In general, a clock synchronous type semiconductor memory device, such as SDRAM, has the burst mode or the continuous mode, in which read data is outputted in a continuous manner or write data is inputted in a continuous manner, in synchronization with a clock. A semiconductor memory device having this kind of the operation mode includes an address counter that generates an internal address following the start address, which is received via an external terminal. Further, the semiconductor memory device sequentially outputs or inputs data indicated by the internal address generated by the address counter.
The burst mode is the operation mode in which data is sequentially read from a plurality of memory cells connected to one word line, or data is written into these memory cells in a sequential manner (for example, disclosed in Japanese Unexamined Patent Application Publication No. Hei 9-106669). In the semiconductor memory device having the burst mode, the number of output data or the number of input data is set in advance as the burst length.
The continuous mode is the operation mode in which data is sequentially read from memory cells respectively connected to a plurality of word lines, or data is written into these memory cells in a sequential manner. In the continuous mode, the burst length is not decided. Data of the entire address can be inputted and outputted continuously by keeping chips to be operated.
FIG. 1 illustrates an example of the read operation and the write operation of the semiconductor memory device having the continuous mode.
The semiconductor memory device inputs or outputs data in synchronization with a rising edge of a clock signal CLK. This kind of the operation mode is generally called “SDR (Single Data Rate) mode”.
In this example, 4-bit parallel data is simultaneously read from a memory array via a 1-bit data terminal DQ, and is latched in a data latch through a data bus line DB. The data latch converts the received parallel data into serial data, and sequentially outputs the data to the data terminal DQ in synchronization with a clock.
In the continuous read operation, a chip enable signal/CE is first activated, and an address signal AD (A05, in this example) that indicates the start address of read data is then provided to a semiconductor memory device (FIG. 1(a)). An internal circuit of the semiconductor memory device continuously activates a column selection signal CL twice in order to connect predetermined bit lines within the memory array to data bus lines DB (DB1, DB2), respectively (FIG. 1(b)). At this time, by activating the column selection signal CL, four read data D04–07 including data D05 corresponding to the address A05, and four read data D08–11 corresponding to addresses A08–11 following the address A05 are transferred to the data bus lines DB1, DB2, and then latched in the data latch (FIGS. 1(c) and 1(d)). That is, data for 8 addresses are latched in the data latch every data terminal DQ.
Thereafter, the latched parallel read data is converted into serial data, and are then sequentially outputted in synchronization with a clock signal CLK (FIG. 1(e)). After the read data D05–07 are all outputted, the column selection signal CL corresponding to next addresses A12–15 is activated, and read data D12–15 are thus latched in the data latch (FIG. 1(f)). The latched read data is converted into serial data, and are then outputted in a sequential manner in synchronization with the clock signal CLK.
On the one hand, in the continuous write operation, after a predetermined clock from the supply of the start address A05, the write data D05, D06, D07 and so on are sequentially provided to the data terminal DQ in synchronization with the clock signal CLK (FIG. 1(g)). Serial write data is converted into parallel data, and are then latched in the data latch. After a predetermined number of the write data is latched in the data latch, the column selection signal CL is activated, and the write data is thus written into memory cells through the data bus line DB (FIGS. 1(h) and 1(i)). In this case, a data bus line DB2 includes negative write data D04. However, the data D04 are not written into the memory cells due to inactivation of the column selection signal CL corresponding to the data D04 or inactivation of a write amplifier corresponding to the data D04.
FIG. 2 shows an example of the switch operation of the word line in the continuous read operation.
In the continuous mode, in order to continuously read data from the memory cells connected to a plurality of the word lines, the word line needs to be switched. In FIG. 2, 00 to n-1 affixed to the clock signal CLK refer to column addresses of output data. That is, in this example, the column address is n types.
A word line WLm is inactivated (FIG. 2(b)) after data Dn-4 to Dn-1 corresponding to the end 4-bit n-4 to n-1 (the end address) of the column address are latched in the data latch (FIG. 2(a)). A next word line WLm+1 is activated after a predetermined period from the inactivation of the word line WLm (FIG. 2(c)).
Such inactivation of the word line WLm and activation of the word line WLm+1 are performed at a timing that is generated within the tip so that it is not synchronized to the clock signal CLK. The column selection signal CL is activated on a 4-block basis. The inactivation of the word line WLm and the activation of the next word line WLm+1 are implemented between the four clock cycles. Meanwhile, whenever the column selection signal CL is activated, the read data is read on a 4-bit basis, and are outputted to the data terminal DQ without being interrupted.
FIG. 3 shows another example of the switch operation of the word line in the conventional continuous read operation.
In this example, the end address n-1 of the column address is provided as the start address (FIG. 3(a)). A word line WLm corresponding to the row address, which is supplied together with the column address, is first activated (FIG. 3(b)). A column selection signal CL corresponding to the end address n-1 is then activated (FIG. 3(c)). Read data Dn-4 to Dn-1 for 4 addresses, including the end address n-1, are read out to a data bus line DB1 from memory cells, and are then latched in the data latch (FIG. 3(d)).
Since the start address is the end address n-1 of the column address, data corresponding to next four column addresses have to be read after the word lines are switched. Accordingly, a second column selection signal CL cannot be activated subsequent to the first column selection signal CL, unlike FIG. 1.
The word line WLm is inactivated in synchronization with a falling edge of the first column selection signal CL (FIG. 3(e)), in the same manner as FIG. 2. A next word line WLm+1 is then activated (FIG. 3(f)).
The second column selection signal CL is activated after the word line WLm+1 is activated (FIG. 3(g)). Furthermore, data D00–D03 corresponding to column addresses 00–03 (word line WLm+1) are latched in the data latch through a data bus line DB2 (FIG. 3(h)). Four clocks are needed from the switch operation of the word lines WL until the data is outputted. For this reason, the first read data D00 corresponding to the word line WLm+1 are outputted by skipping 3 clocks starting from the clock signal that outputs the data Dn-1 (FIG. 3(i)).
As such, in the continuous read operation, in the case where an address adjacent to the end address of the column address is designated as the start address, an non-output period occurs from the time when data corresponding to the first word line WLm are outputted until the time when data corresponding to the next word line WLm+1 are outputted.
The semiconductor memory device has to output a wait signal/WAIT in order to transfer the non-output period of data to a controller that has access to itself (FIG. 3(j)). Accordingly, the controller must include a control circuit of the wait signal/WAIT. Control of the semiconductor memory device by the controller, however, adds complication. Furthermore, since terminals for the wait signal/WAIT are necessary in the semiconductor memory device and the controller, the chip size also increases.
FIG. 4 illustrates still another example of the switch operation of the word line in the conventional continuous read operation.
In this example, an address, which is located one earlier than the end column address n-1, is supplied as the start address (FIG. 4(a)). At this time, the semiconductor memory device is required to output the wait signal/WAIT for two clocks (FIG. 4(b)).
Generally, in the case where k-bit parallel data is read once from the memory array or written into the memory array immediately, the semiconductor memory device has to output the wait signal/WAIT in order to delay the output of the read data, when the start address is located after the end column address (k-1).